This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits and pulse generators.
One aspect of designing an integrated circuit (IC) is timing. Timing is the relationship between two or more signals with respect to time. A particular signal may need to be established at the input of a latch, before the latch is opened. This example is often called xe2x80x9csetup timexe2x80x9d. Another example of a timing issue is a xe2x80x9cracexe2x80x9d condition. A race condition may occur when a signal propagates into a memory element (e.g. a latch) before it should. The memory element in this case may close too slowly while data from another circuit transitions fast enough to be stored in the memory. The data from the other circuit should have been stored on the next clock cycle. In some cases where timing is an important issue, a voltage pulse is created that may activate a circuit for a time corresponding to the width of the pulse. The width of the pulse in time may be critical. The width of the pulse should be well defined over process variations as well as variations in temperature and voltage. An example of a circuit where a pulse may be used to control timing is a RAM (Random Access Memory) device.
RAM cells store digital bit values and allow those values to be read at a later time. A RAM cell also allows previous stored values to be written over by new digital bit values. A DRAM (Dynamic Random Access Memory) cell, and an SRAM (Static Random Access Memory) cell are examples of RAM cells that are used in integrated circuit designs. A SRAM cell maintains data without a refresh cycle while a DRAM cells must be refreshed periodically. SRAM cells are used in many electronic applications requiring data storage such as in an internal cache memory of a microprocessor. DRAM cells and SRAM cells may be used to create stand-alone DRAM and SRAM integrated circuits. RAM cells generally comprise one or more storage elements, and additional circuitry to allow charge to transfer from the storage elements to bitlines. Bitlines are electrically connected to a group of RAM cells and to circuitry at the ends of the bitlines for reading writing, and prechanging the bitlines. The value of the digital bit stored in the storage element is developed on the bitlines by transfering charge from a storage element to the bitlines. Transferring charge from a storage element to the bitlines causes the voltage on the bitlines to change. The rate of change in voltage between the bitlines may be relatively slow due to the number of RAM cells electrically connected to the bitlines and the current sinking capability of an individual RAM cell. In order to avoid unacceptably long delays created by waiting for a RAM cell to cause a nearly full rail-to-rail (power supply to power supply) voltage swing on the bitlines, a sense-amp may be connected to the bitlines to amplify a smaller voltage swing generated by the RAM cell. A sense-amp is capable of amplifying the signal developed on the bitlines after a relatively small signal has been developed on the bitlines by a RAM cell. The sense-amp compares the two bitlines and determines which has a larger voltage when there is only a small voltage differential between them. The sense-amp compares the voltage differential on the two bitlines after the sense amp is triggered by a delayed clock signal. The delay in the clock signal may be timed by several methods. One method is to use a signal from a selected wordline. A wordline is a signal that activates transfer gates on a row of RAM cells. After these transfer gates are activated, differential signal is developed on each bitline. Another method used to create a delay is to use an appropriate number of inverters connected in series. If the delayed clock signal goes active too early, the sense-amp may not be able to xe2x80x9csensexe2x80x9d the correct digital signal. If the delay of the delayed clock signal is delayed too long, the access time of the RAM may not be optimal
In addition to optimally timing the start of a delayed signal to a sense-amp, it is important to limit the time that the sense-amp is activated. If a sense-amp is active for a relatively long period of time, it may cause higher peak power for circuitry with one or more sense-amps. It may also cause an increase in the offset voltage of sense-amps that are designed in SOI (Silicon on Insulator). Sense-amps designed in SOI may have transistors with different Vt""s (threshold voltages) due to charge accumulating on the body of these transistors. Since these transistors may have different bias conditions while the sense-amp is enabled, an offset voltage may be developed. In order to overcome an offset voltage developed by this mechanism, precharge circuitry must be active for a longer period of time or must have larger transistors. Either case is not desired in the design of RAMs. There is a need in the art for a well-timed, edge-triggered, self-resetting pulse generator. The apparatus described in this invention, an edge-triggered, self-resetting pulse generator, meets this need.
An embodiment of the invention provides an edge-triggered, self-resetting pulse generator. A negative-edge signal (a transition from a high voltage to a lower voltage) is presented to one input of a two-input NOR gate and to the input of a circuit with three inverters in series. The output of the circuit with three inverters in series is connected to the second input to the NOR gate. The combination of the circuit with three inverters and the NOR gate creates a positive pulse that drives the gate of an NFET (N-type field effect transistor). The pulse on the gate of the NFET pulls the input of a latch to ground. The latch drives, through a buffer, the output of the pulse generator to a high value. The high value is maintained until feedback from the output of the pulse generator drives the input of the latch high. The output of the pulse generator is then driven low and is held low until another negative edge signal is presented at the input of the pulse generator. The feedback path includes several delay elements in series that drive the gate of a PFET (P-type Field Effect Transistor). The PFET drives the input of the latch high when the gate of the PFET is driven low. The feedback enables the pulse generator to be self-resetting. The invention may be easily adapted to other technologies used to fabricate integrated circuits.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.